This invention relates to circuitry that enables registers with limited asynchronous functions to perform asynchronous loading operations.
Programmable logic devices are integrated circuits that are programmable by a user to perform various logic functions. At their most basic level, programmable logic devices contain programmable components, such as erasable programmable read-only (EPROM) transistors, electrically erasable programmable read-only (EEPROM) transistors, random access memory (RAM) transistors or cells, fuses, and antifuses. Higher level functions are provided by organizing the programmable components into groups of components. The groups of components are electrically connected to one another by programmable interconnections.
Programmable logic devices generally contain registers for temporarily holding data during logic operations. In order to conserve real estate on the die and to conserve circuit resources, it is sometimes necessary to reduce the hard-wired capabilities of such registers. For example, a register's asynchronous set function may be eliminated. Because many registers are used in the programmable logic device, even a small reduction in the real estate and circuit resources used by each register can result in a considerable savings in terms of the overall cost and complexity of the programmable logic device.
Registers with such limited asynchronous capabilities are mainly used to perform synchronous operations, so the loss of the asynchronous function is not of critical importance in most programmable logic device applications. Nonetheless, many logic designers would like to have both the asynchronous set and asynchronous clear functions available. Such an arrangement makes asynchronous loading possible, because an asynchronous set is equivalent to an asynchronous load of a 1 and an asynchronous clear is equivalent to an asynchronous load of a 0. In a register with asynchronous loading capabilities, a desired bit can be loaded into a register between clock cycles to override or replace the bit that would normally be contained in the synchronous logic stream through the register.
Although the ability to asynchronously load registers is desirable, real estate and circuit resource considerations may nevertheless dictate that registers in certain programmable logic devices have only limited asynchronous functions (e.g., only asynchronous clear capabilities). It is therefore an object of the present invention to provide an arrangement that allows registers that have limited asynchronous functions with the ability to perform asynchronous loading.